1. Field of the Invention
The present invention relates to a method of fabricating a memory cell in a semiconductor device, and more particularly, to a method of fabricating a memory cell having a dual floating gate in a semiconductor device.
2. Discussion of the Related Art
FIG. 1 is a cross-sectional diagram of the Flasys memory cell according to a related art.
Referring to FIG. 1, a floating gate 2, an oxide-nitride-oxide (ONO) layer 7, and a control gate 1 are stacked on a substrate 5.
And, a poly-metal dielectric 6 is formed on the substrate 5 including the floating gate 2, the ONO layer 7, and the control gate 1.
An operational principle of the related art memory cell is explained as follows.
First of all, in order to store data, capacitance coupling occurs in the ONO layer 7 by a positive voltage applied to the control gate 1 to bring about a turned-on state so that electrons can be sucked into the floating gate 2 by a current between a source 3 and a drain 4.
In order to erase data, a negative voltage is applied to the control gate 1 and a positive voltage is applied to the substrate 5, whereby the electrons stored in the floating gate 2 are drained out to the substrate 5.
Such a data storing/erasing method is called a single type method.
However, the single type method stores/erases data in/from the single gate 2 only, thereby putting a limitation on memory capacity unless a critical dimension of the device is increasingly lowered for higher degree of integration.
And, it is impossible to enable dichotomization on storing data.